1. Field of Invention
The present invention relates to the field of liquid crystal display technology, and more particularly to a liquid crystal display for a GOA (Gate Driver on Array, an array substrate row driver) circuit and a display device.
2. Description of Prior Art
In an active liquid crystal display, each pixel has a thin film transistor (TFT), and its gate (Gate) is connected to the horizontal scanning line, a drain (Drain) is connected to the data line, and the source (Source) is connected to the pixel electrode. Applying a sufficient voltage to the scanning line, so that all the TFTs on the scanning line will open, the display signal voltage of the data line is written into the pixel electrode through the TFT, thereby controlling different LCD transmittance and thus controlling the color effect.
At present, the scanning lines of the active liquid crystal display panel are driven by external ICs (integrated chips) connected with the active liquid crystal display panel. The external ICs are configured to control the stepwise charge of each level of the scanning lines and discharge of each level of the scanning lines.
In the GOA technique, namely Gate Driver on Array (array substrate row driver) technology, the driving circuit of the scanning lines can be formed on the panel around an area of the display area by using the original LCD panel manufacturing process, so that the GOA technique can accomplish the driving of the scanning lines by replacing the external ICs. The GOA technique can reduce the binding process of external ICs, and might improve productivity and reduce production costs; it also makes the LCD panel be more suitable for production with narrow borders or even no borders around the display products.
Existing GOA circuits generally include a plurality of shift register units, each shift register unit corresponding to drive a scanning line. The shift register unit includes a pull-up circuit (Pull-up part), a pull-up control circuit (Pull-up control part), a down transfer circuit (Transfer Part), a pull-down circuit (Key Pull-down Part) and a pull-down sustain circuit (Pull-down Holding Part), and a bootstrap (Boast) capacitor is responsible for raising potential. The Pull-up circuit is mainly responsible for making the clock signal (Clock) to output as a gate (Gate) signal; a pull-up control circuit is configured to control the opening time of the pull-up circuit, and is usually connected to a downstream signal or a Gate signal of a previous level of shift register; the pull-down circuit is responsible for pulling the Gate signal down to low potential firstly, in other words, when the Gate signal is closed; the pull-down circuit is further responsible for holding the output signal of the Gate and Gate signal point of the pull-up circuit (usually called Q point) in the closed state (negative potential). There are usually two drop maintain modules working alternatively; the bootstrap capacitor (C boast) is responsible for secondary lifting of Q point, it is a good to an output of G(N) of the pull-up circuit.
FIG. 1 is a circuit diagram of a GOA circuit of a prior art. A shift register comprises a pull-up control circuit 100, a pull-up circuit 200, a downstream circuit 300, a pull-down circuit 400, a bootstrap capacitor 500, a first pull-down sustain circuit 600, a second pull-down sustain circuit 700, and a bridge circuit 800. The first pull-down sustain circuit 600, the second pull-down sustain circuit 700, and the bridge circuit 800 constitute a design of 3-stages of a resistance voltage division.
The bridge circuit 800 is responsible for adjusting the potentials of P(N) and K(N) mainly by TFT T55. A gate of the TFT T55 couples with Q(N), a drain of the TFT T55 couples with P(N), and a source of the TFT T55 couples with K(N). During operation, the gate of TFT T55 is open to make the potentials of P(N) and K(N) similar and under a close state. The low potentials of low frequency signals LC1 and LC2 are less than VSS, which adjusts the potentials of P(N) and K(N) to be less than VSS during operation and make sure that Vgs of TFTs T32, T33 used to pull down G(N) point and Vgs of TFTs T42, T43 used to pull down Q(N) are less than 0 volts, which has a better performance to prevent the current leakage of G(N) and Q(N).
The first pull-down sustain circuit 600 and the second pull-sown sustain circuit 700 are based on a symmetric design, which accomplishes the functions below: first, during operation, the first pull-down sustain circuit 600 (or the second pull-sown sustain circuit 700) serves as a big-resistance and is in a close state, the second pull-sown sustain circuit 700 (or the first pull-down sustain circuit 600) serves as a small-resistance and is in an open state, and the bridge circuit 800 serves as a small-resistance and is in the open state to make P(N) and K(N) in a low potential state, and ensures the lifting of Q(N) and the output of G(N); second, during non-operation, both the first pull-down sustain circuit 600 and the second pull-sown sustain circuit 700 serve as small-resistances and are in the open state and the bridge circuit 800 serves as large resistance and is in the close state to accomplish the high and low potentials and alternation of P(N) and K(N). A gate of a TFT T54 couples with LC2, a drain of the TFT T54 couples with LC2, and a source of the TFT T54 couples with P(N). A gate of a TFT T64 couples with LC1, a drain of the TFT T64 couples with LC2, and a source of the TFT T64 couples with L(N). The TFTs T54, T64 are called balanced TFTs, which are used to adjust the resistance voltage division and a rapid discharge while switching signals. A gate of a TFT T52 couples with Q(N), a drain of the TFT T52 couples with S(N), and a source of the TFT T52 couples with VSS. A gate of a TFT T62 couples with Q(N), a drain of the TFT T62 couples with T(N), and a source of the TFT T62 couples with VSS. The TFTs T52, T62 are used to pull down S(N) and T(N) during operation.
By using the shift register unit applied to the 3-stages resistance voltage division, which is constituted by the first pull-down sustain circuit 600, the second pull-down sustain circuit 700, and the bridge circuit 800, high temperature stability and long-time operation reliability of the pull-down sustain circuit are increased, the switch of P(N) and K(N) is accomplished by using a low frequency signal, and the electricity leakage of G(N) and Q(N) is reduced as low as possible by pull down of the potentials of P(N) and K(N) to during operation. During non-operation, one of P(N) and K(N) is closed to the low potential of LC at a low potential, because the low potential of LC is lower than VSS, the TFTs T32/T42 or the TFTs T33/T43 are in a negative potential recovery state with half of the time needed to control the potential of the negative potential by adjusting the low potential pf the low frequency signal, and a risk of malfunction of the pull-down sustain circuit is effectively decreased.
However, the existing GOA circuits have mainly adopted a theory of shift registers; a transmission of stepwise signals generally accomplishes down transfer by the scanning line G(N), a loading of scanning line G(N) increases, wiring is complicated, and a risk of disconnection exists.
Furthermore, the conventional GOA circuits are designed for a one-direction scanning, with a two-directions scanning being impossible.